The invention relates to clock recovery circuitry for recovering a clock signal from a data signal.
When receiving an asynchronous data signal, a clock signal is usually recovered from the received data signal and used to sample the data signal. Known clock recovery circuits use a phase locked loop to lock the phase of a reference clock to the phase of the received data signal, in order to recover a clock signal.
A problem in known clock recovery circuits is that it may take many clock cycles for the phased locked loop to lock onto the data signal, in particular if high speed data signals are being received. If data is received in bursts, then the phase locked loop may need to lock onto each burst of data separately, which may result in a relatively large proportion of the total transmission time being used for clock recovery.
In order to increase the speed with which a phase locked loop locks onto a data signal, it is possible to increase the loop gain of the phase locked loop. However, this may have the effect of increasing jitter in the recovered clock signal. Furthermore, in the case of high speed data signals, it may still take many clock cycles before the phase locked loop is locked onto the data signal.